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TC90A66F 2001-06-07 1 toshiba cmos digital integrated circuit silicon monolithic t c 9 0 a 6 6 f pap/pip/pop controller for wide-screen tvs (pal/ntsc) with built-in ad and da converters (adc/dac), the TC90A66F is a picture-and-picture (pap)/picture-in-picture (pip)/picture-out-picture (pop) controller ic for pal and ntsc formats. it is used in combination with field memory, video signal processor ics. the TC90A66F enables a variety of picture display functions. the ic is optimal to provide wide-screen tvs with additional functionality. features ? two-channel 8-bit adc, three-channel 8-bit dac, clamp circuit, and multiplexer integrated on single chip ? external field memory recommended memory: msm51v8221, msm51v8222 (by oki) ? picture display functions pap display half-picture left and right sides of 16:9 screen (motion picture mode or still mode selectable) pip display 4:3 or 16:9 aspect ratio (motion picture mode or still mode selectable) pop display 4:3 aspect ratio (3 pictures in still mode, 1 picture in motion picture mode and 2 pictures in still mode, or strobe mode selectable) multi-picture still display of up to 24 still pictures per screen channel search 9, 12, or 16 picture search (still mode, strobe mode, or 1 picture in motion picture mode selectable) ? variable frame width and frame color ? built-in horizontal and vertical filters ? i 2 c bus for micro controller interface ? 3.3-v single power supply ? package: qfp144 weight: 4.64 g (typ.) preliminar y
TC90A66F 2001-06-07 2 pin assignment adv dd yins iins adv ss adv dd qins vrt y adv ss vrb y vrtc vrbc adv dd yine iine adv ss av dd qine av ss v dd cnt2 cnt1 cnt0 clamp tin9 tin8 tin7 tin6 tin5 tin4 tin3 tin2 tin1 tin0 wvde whde v ss 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 adbias 108 vref 107 vb1 106 vb2 105 qout 104 dav dd 103 iout 102 dav ss 101 yout 100 dav dd 99 v ss 98 cnt3 97 cnt4 96 cnt5 95 cnt6 94 t100 93 t101 92 t102 91 t103 90 t104 89 t105 88 t106 87 t107 86 v dd 85 test0 84 test1 83 test2 82 test3 81 test4 80 sda 79 scl 78 v ss 77 sacn 76 sadsel 75 iicnr 74 teso 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 wcke whrefe v dd hrst moh wvds whds v ss wcks whrefs v dd ewmck v ss wmck v ss ewien ewen ewrst wien wen wrst wdac7 wdac6 wdac5 wdac4 wdac3 wdac2 wdac1 wdac0 v ss wday7 wday6 wday5 wday4 wday3 wday2 timrst 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 pwrst hyojun kays ys rvd rhd v dd rck rhref rmcki v ss rmck errst eren rrst ren rday7 rday6 rday5 rday4 rday3 rday2 rday1 rday0 v dd rdac7 rdac6 rdac5 rdac4 rdac3 rdac2 rdac1 rdac0 wday0 wday1 TC90A66F
TC90A66F 2001-06-07 3 system block diagram scl sda yin cin yin cin yin cin yin cin sda scl sda scl y1in i1in q1in y2in i2in q2in ys yout iout qout yout iout qout hd vd sub vcd1 ta1270af pap/pip/pop TC90A66F yout iout qout pll circuit 2m memory * 2 msm51v8221 y i q sub vcd2 ta1270af yout iout qout hd vd pll circuit yins iins qins ys wvds whds rhd rvd yine iine qine wvde whde whrefs wcks whrefe wcke pll circuit rhref rck rdac rda y rmc k wdac wda y wmc k sda scl -com sub picture (s) image input signal sub picture (e) image input signal output signal
TC90A66F 2001-06-07 4 TC90A66F block diagram scl sda yout iout qout main -com iic bus a c l m p m p x c l m p m p x wday 7 to 0 rdac 7 to 0 rmcki wdac 7 to 0 rday 7 to 0 wmck 1200 fh (4m/2m) wrst weny wenc wie rrst ren rmck 1200 fh (4m/2m) a/d a/d horizontal filter vertical filter vertical filter line memory line memory y/iq separator sub picture s generates system clock for write 2400 fh (4m/2m) generates system clock for write 2400 fh (4m/2m) generates system clock for read 2400 fh (4m/2m) odd/even detector circuit generates control signal for write generates control signal for read a control signals for write control signals for read 2m memory (msm51v8221) in out (not required in 2m mode) sub picture e main picture rhref rck rhd rvd whref wcks whds wvds whrefe wcke whde wvde output processor (frame color select, y/c phase adjustment) stand processor code processor d/a d/a d/a picture display switch signal memory use switch signal 2m memory (msm51v8221) in out vref vb1 vb2 ys pwrst moh yin (s) iin (s) qin (s) yin (e) iin (e) qin (e)
TC90A66F 2001-06-07 5 pin functions (144-pin qfp) pin number pin name i/o function 1 adv dd ? power supply for a/d (3.3 v) 2 yins i a/d y signal (s system) input 3 adv ss ? gnd for a/d 4 iins i a/d i signal or r-y signal (s system) input 5 adv dd ? power supply for a/d (3.3 v) 6 qins i a/d q signal or b-y signal (s system) input 7 adv ss ? gnd for a/d 8 vrty i reference voltage for a/d y signal (top) 9 vrby i reference voltage for a/d y signal (bottom) 10 vrtc i reference voltage for a/d i, q signal (top) 11 vrbc i reference voltage for a/d i, q signal (bottom) 12 adv dd ? power supply for a/d (3.3 v) 13 yine i a/d y signal (e system) input 14 adv ss ? gnd for a/d 15 iine i a/d i signal or r-y signal (e system) input 16 av dd ? power supply for analog circuit (3.3 v) 17 qine i a/d q signal or b-y signal (e system) input 18 av ss ? gnd for analog circuit 19 v dd ? power supply (3.3 v) 20 cnt2 o test output pin 21 cnt1 o test output pin 22 cnt0 o test output pin 23 clamp o clamp signal monitor output 24 tin9 i test input pin (connect to gnd) 25 tin8 i test input pin (connect to gnd) 26 tin7 i test input pin (connect to gnd) 27 tin6 i test input pin (connect to gnd) 28 tin5 i test input pin (connect to gnd) 29 tin4 i test input pin (connect to gnd) 30 tin3 i test input pin (connect to gnd) 31 tin2 i test input pin (connect to gnd) 32 tin1 i test input pin (connect to gnd) 33 tin0 i test input pin (connect to gnd) 34 wvde i (e system) vertical sync signal input (it can be inverted using i 2 c bus) (note1) 35 whde i (e system) horizontal sync signal input (it can be inverted using i 2 c bus) (note1) 36 v ss ? gnd 37 wcke i (e system) system clock input (note1) 38 whrefe i/o (e system) pll phase comparison output 39 v dd ? power supply (3.3 v) 40 hrst o unit adjusting pin 41 moh o memory use switch signal [(ycs (l) :/ TC90A66F (h)) note1: supports 5 v interface.
TC90A66F 2001-06-07 6 pin number pin name i/o function 42 wvds i (s system) vertical sync signal input (it can be inverted using i 2 c bus) (note1) 43 whds i (s system) horizontal sync signal input (it can be inverted using i 2 c bus) (note1) 44 v ss ? gnd 45 wcks i (s system) system clock input (note1) 46 whrefs o (s system) pll phase comparison output 47 v dd ? power supply (3.3 v) 48 ewmck o (e system) write clock output for field memory 49 v ss ? gnd 50 wmck o (s system) write clock output for field memory 51 v ss ? gnd 52 ewien o (e system) field memory input enable 53 ewen o (e system) field memory write enable 54 ewrst o (e system) field memory write reset 55 wien o (s system) field memory input enable 56 wen o (s system) field memory write enable 57 wrst o (s system) field memory write reset 58 wdac7 o iq or sub picture (e system) signal output (field memory write signal/msb) 59 wdac6 o iq or sub picture (e system) signal output (field memory write signal/ : ) 60 wdac5 o iq or sub picture (e system) signal output (field memory write signal/ : ) 61 wdac4 o iq or sub picture (e system) signal output (field memory write signal/ : ) 62 wdac3 o iq or sub picture (e system) signal output (field memory write signal/ : ) 63 wdac2 o iq or sub picture (e system) signal output (field memory write signal/ : ) 64 wdac1 o iq or sub picture (e system) signal output (field memory write signal/ : ) 65 wdac0 o iq or sub picture (e system) signal output (field memory write signal/lsb) 66 v ss ? gnd 67 wday7 o y or sub picture (s system) signal output (field memory write signal/msb) 68 wday6 o y or sub picture (s system) signal output (field memory write signal/ : ) 69 wday5 o y or sub picture (s system) signal output (field memory write signal/ : ) 70 wday4 o y or sub picture (s system) signal output (field memory write signal/ : ) 71 wday3 o y or sub picture (s system) signal output (field memory write signal/ : ) 72 wday2 o y or sub picture (s system) signal output (field memory write signal/ : ) 73 wday1 o y or sub picture (s system) signal output (field memory write signal/ : ) 74 wday0 o y or sub picture (s system) signal output (field memory write signal/lsb) 75 rdac0 i iq or sub picture (e system) signal input (field memory read signal/lsb) (note1) 76 rdac1 i iq or sub picture (e system) signal input (field memory read signal/ : ) (note1) 77 rdac2 i iq or sub picture (e system) signal input (field memory read signal/ : ) (note1) 78 rdac3 i iq or sub picture (e system) signal input (field memory read signal/ : ) (note1) 79 rdac4 i iq or sub picture (e system) signal input (field memory read signal/ : ) (note1) 80 rdac5 i iq or sub picture (e system) signal input (field memory read signal/ : ) (note1) 81 rdac6 i iq or sub picture (e system) signal input (field memory read signal/ : ) (note1) 82 rdac7 i iq or sub picture (e system) signal input (field memory read signal/msb) (note1) 83 v dd ? power supply (3.3 v) 84 rday0 i y or sub picture (s system) signal input (field memory read signal/lsb) (note1) note1: supports 5 v interface.
TC90A66F 2001-06-07 7 pin number pin name i/o function 85 rday1 i y or sub picture (s system) signal input (field memory read signal/ :) (note1) 86 rday2 i y or sub picture (s system) signal input (field memory read signal/ : ) (note1) 87 rday3 i y or sub picture (s system) signal input (field memory read signal/ : ) (note1) 88 rday4 i y or sub picture (s system) signal input (field memory read signal/ : ) (note1) 89 rday5 i y or sub picture (s system) signal input (field memory read signal/ : ) (note1) 90 rday6 i y or sub picture (s system) signal input (field memory read signal/ : ) (note1) 91 rday7 i y or sub picture (s system) signal input (field memory read signal/msb) (note1) 92 ren o (s system) field memory read enable 93 rrst o (s system) field memory read reset 94 eren o (e system) field memory read enable 95 errst o (e system) field memory read reset 96 rmck o (s/e system) read clock output for field memory 97 rmcki i rmck input (phase adjustment) 98 v ss ? gnd 99 rhref o pll phase comparison output for main picture 100 rck i system clock input for main picture (note1) 101 v dd ? power supply (3.3 v) 102 rhd i horizontal sync single input for main picture (it can be inverted using i 2 c bus) (note1) 103 rvd i vertical sync single input for main picture (it can be inverted using i 2 c bus) (note1) 104 ys o ys signal output 105 kays o wallpaper ys signal output 106 hyojun o standard/non-standard signal output [standard (l)/non-standard (h)] 107 pwrst i system reset input [reset (l)] 108 timrst i test reset input [reset (h)/normal (l)] 109 teso o test monitor output 110 iicnr i i 2 c bus noise reduction circuit [on (h)/off (l)] 111 sadsel i main/sub sub address switch [main (h)/sub (l)] 112 sacn o i 2 c bus acknowledge output pin 113 v ss ? gnd 114 scl i i 2 c bus serial clock input (note1) 115 sda i/o i 2 c bus serial data input (in)/acknowledge (out) (note1) 116 test4 i test input pin (connect to gnd) 117 test3 i test input pin (connect to gnd) 118 test2 i test input pin (connect to gnd) 119 test1 i test input pin (connect to gnd) 120 test0 i test input pin (connect to gnd) 121 v dd ? power supply (3.3 v) 122 tio7 i/o test input/output pin (normally, open) 123 tio6 i/o test input/output pin (normally, open) 124 tio5 i/o test input/output pin (normally, open) 125 tio4 i/o test input/output pin (normally, open) 126 tio3 i/o test input/output pin (normally, open) 127 tio2 i/o test input/output pin (normally, open) note1: supports 5 v interface.
TC90A66F 2001-06-07 8 pin number pin name i/o function 128 tio1 i/o test input/output pin (normally, open) 129 tio0 i/o test input/output pin (normally, open) 130 cnt6 o test output pin 131 cnt5 o test output pin 132 cnt4 o test output pin 133 cnt3 o test output pin 134 v ss ? gnd 135 dav dd ? power supply for d/a (3.3 v) 136 yout o y signal output 137 dav ss ? d/a gnd 138 iout o i signal or r-y signal output 139 dav dd ? power supply for d/a (3.3 v) 140 qout o q signal or b-y signal output 141 vb2 ? d/a bias 142 vb1 ? d/a bias 143 vref i d/a reference bias (supply 2.3 v) 144 adbias ? a/d bias
TC90A66F 2001-06-07 9 pin description pin number pin name function 2 yins y-signal (s system) analog input input amplitude is 1 v p-p typical. 4 iins i or r-y signal (s system) analog input input amplitude is 1 v p-p typical. 6 qins q or b-y signal (s system) analog input input amplitude is 1 v p-p typical. 8 vrty high-level reference power supply pin for adc y signal. sets the upper limit of the adc dynamic range. fixed to 2.2 v (typ.) by internal resistance type potential division. connect 0.1 f bypass capacitor between the pin and gnd. 9 vrby low-level reference power supply voltage for adc y signal. sets the lower limit of the adc dynamic range. fixed to 1.1 v (typ.) by internal resistance type potential division. connect 0.1 f bypass capacitor between the pin and gnd. 10 vrtc high-level reference power supply pin for adc iq signal. sets the upper limit of the adc dynamic range. fixed to 2.2 v (typ.) by internal resistance type potential division. connect 0.1 f bypass capacitor between the pin and gnd. 11 vrbc low-level reference power supply voltage for adc iq signal. sets the lower limit of the adc dynamic range. fixed to 1.1 v (typ.) by internal resistance type potential division. connect 0.1 f bypass capacitor between the pin and gnd. 13 yine y signal (e system) analog input input amplitude is 1 v p-p typical. 15 iine i or r-y signal (e system) analog input input amplitude is 1 v p-p typical. 17 qine q or b-y signal (e system) analog input input amplitude is 1 v p-p typical. 23 clamp clamp signal monitor output pin. can monitor clamp pulse start/stop position set at 24h or 25h. outputs signal for the last data (s or e system) transfer. 34 wvde (e system) vertical sync signal input pin. (it can be inverted using i 2 c bus) inputs vertical sync signal from vcd for sub picture e. it is composing 5 v interface. for negative polarity input, set sub address [26h: evinv] to l (negative polarity input). 35 whde (e system) horizontal sync signal input pin. (it can be inverted using i 2 c bus) inputs horizontal sync signal from vcd for sub picture e. it is composing 5 v interface. for negative polarity input, set sub address [26h: ehinv] to l (negative polarity input). 37 wcke (e system) write clock input pin. inputs from the external pll circuit. it is composing 5 v interface. inputs 2400 fh for both 4m and 2m memory mode. 38 whrefe (e system) pll phase comparison output. the href signal obtained by the i/n divider circuit or the phase comparison result of sub picture (e) horizontal sync signal. 40 hrst unit adjustment (ws/we/r switch able) 41 moh external field memory use signal output pin. output amplitude is 3.3 v p-p typical. setting sub address [21h: moh] to h uses TC90A66F; setting to l sets all memory output pins to hi-z. 42 wvds (s system) vertical sync signal input pin. (it can be inverted using i 2 c bus) inputs vertical sync signal from vcd for sub picture s. it is composing 5 v interface. for negative polarity input, set sub address [27h: wvinv] to l (negative polarity input). 43 whds (s system) horizontal sync signal input pin. (it can be inverted using i 2 c bus) inputs horizontal sync signal from vcd for sub picture s. it is composing 5 v interface. for negative polarity input, set sub address [27h: whinv] to l (negative polarity input). 45 wcks (s system) write clock input pin. inputs from the external pll circuit. it is composing 5 v interface. inputs 2400 fh for both 4m and 2m memory mode.
TC90A66F 2001-06-07 10 pin number pin name function 46 whrefs (s system) pll phase comparison output. the href signal obtained by the i/n divider circuit or the phase comparison result of sub picture (s) horizontal sync signal. this signal is used to control the external vco voltage. 48 ewmck outputs sub picture e write clock to external field memory. output amplitude is 3.3 v p-p typical. 50 wmck outputs sub picture s write clock to external field memory. output amplitude is 3.3 v p-p typical. 52 ewien control signal output pin for external field memory (sub picture e). output amplitude is 3.3 v p-p typical. 53 ewen control signal output pin for external field memory (sub picture e). output amplitude is 3.3 v p-p typical. 54 ewrst control signal output pin for external field memory (sub picture e). output amplitude is 3.3 v p-p typical. 55 wien control signal output pin for external field memory (sub picture s). output amplitude is 3.3 v p-p typical. 56 wen control signal output pin for external field memory (sub picture s). output amplitude is 3.3 v p-p typical. 57 wrst control signal output pin for external field memory (sub picture s). output amplitude is 3.3 v p-p typical. 58 to 65 wdac7-0 output signal to write to external field memory. (i, q or e system). output amplitude is 3.3 v p-p typical. connect only when using 4m memory. msb: wdac7, lsb: wdac0 67 to 75 wday7-0 output signal to write to external field memory. (y or s system). output amplitude is 3.3 v p-p typical. msb: wday7, lsb: wday0 75 to 82 rdac0-7 input signal to read from external field memory (i, q or e system). it is composing 5 v interface. connect only when using 4m memory. msb: rdac7, lsb: rdac0 84 to 91 rday0-7 input signal to read from external field memory (y or s system). it is composing 5 v interface. msb: rday7, lsb: rday0 92 ren control signal output pin for external field memory (sub picture s). output amplitude is 3.3 v p-p typical. 93 rrst control signal output pin for external field memory (sub picture s). output amplitude is 3.3 v p-p typical. 94 eren control signal output pin for external field memory (sub picture e). output amplitude is 3.3 v p-p typical. 95 errst control signal output pin for external field memory (sub picture e). output amplitude is 3.3 v p-p typical. 96 rmck outputs read clock to external field memory. output amplitude is 3.3 v p-p typical. outputs 1200 fh for both 4m and 2m memory. 97 rmcki rmck phase adjustment input pin. inputs rmck.
TC90A66F 2001-06-07 11 pin number pin name function 99 rhref pll phase compare output pin for main picture. the href signal obtained by the i/n divider circuit or the phase comparison result of rhd signal. this signal is used to control the external vco voltage. 100 rck read clock input pin. it is composing 5 v interface. inputs from the external pll circuit. inputs 2400 fh for both 4m and 2m memory. 102 rhd horizontal sync signal input pin for main picture (read). inputs horizontal sync signal from vcd for main picture. it is composing 5 v interface (negative polarity input). for negative polarity input, set sub address [28h: rhinv] to non-in version (l). 103 rvd vertical sync signal input pin for main picture (read). inputs vertical sync signal from vcd for main picture. it is composing 5 v interface (negative polarity input). for negative polarity input, set sub address [28h: rvinv] to non-inversion (l). 104 ys main/sub picture switch timing signal output pin. output amplitude is 3.3 v p-p typical. when the ys signal is high, displays sub picture. 105 kays wallpaper ys signal output. 106 hyojun standard/non-standard signal output pin [standard (l)/non-standard (h)] 107 pwrst system reset input pin. when low input, it carries out the reset. at least 1 v is required as reset duration. 110 iicnr i 2 c bus noise reduction circuit setting pin. when set to on (connect to v dd ), data are latched once by the internal clock, then written to register. when set to off (connect to gnd), data are written to register directly. 111 sadsel sub address of main/sub picture switching pin. [main (h)/sub (l)] normally, set to l (enables sub addresses 00h to 7fh). 112 sacn i 2 c bus acknowledge output pin. 114 scl i 2 c bus serial clock input pin. it is composing 5 v interface. 115 sda i 2 c bus serial data input/acknowledge output pin. it is composing 5 v interface. 136 yout y signal output pin. output amplitude is 0.9 v p-p typical. 138 iout i signal output pin. output amplitude is 0.9 v p-p typical. 140 qout q signal output pin. output amplitude is 0.9 v p-p typical. 141 to 142 vb2-1 bias pin for dac. connect a 0.1 f bypass capacitor between the pins and gnd. 143 vref dac reference voltage input pin. reference voltage is 2.3 v typical. 144 adbias bias pin for adc. connect a 0.1 f bypass capacitor between the pin and agnd.
TC90A66F 2001-06-07 12 example of typical a/d converter input level for luminance signal example of typical a/d converter input level for chrominance signal 1.1 v 2.2 v 1.1 v 100 (ire) 0 (ire) 0.27 v 0.71 v ? 40 (ire) 255 228 63 0 dec. hex ffh e4h 3fh 00h signal amplitude: 1.0 v p-p (100% white) pedestal clamp value 1.1 v 2.2 v 1.1 v 0.5 v 0.5 v 255 251 21 0 dec. hex ffh ebh 15h 00h signal amplitude: 1.0 v p-p reference potential clamp value 136 88h
TC90A66F 2001-06-07 13 example of typical d/a converter output level for luminance signal example of typical d/a converter output level for chrominance signal 1.0 v 3.3 v 2.3 v 100 (ire) 0 (ire) 0.25 v 0.64 v ? 40 (ire) 255 228 63 0 dec. hex ffh e4h 3fh 00h signal amplitude: 0.9 v p-p (100% white) 1.1 v 3.3 v 2.3 v 0.45 v 0.45 v 255 243 13 0 dec. hex ffh e3h 0dh 00h signal amplitude: 0.9 v p-p 128 80h 3.25 v 2.8 v 2.35 v
TC90A66F 2001-06-07 14 picture display function sub picture (s) main picture (e) 2-picture (pap) display 4:3 aspect ratio (full picture can be displayed) sub picture (s), (e): motion or still (pictures can be exchanged) sub picture (s) 1-picture display (full picture can be used) multiple picture search using the whole screen 12 or 9 still pictures, strobe display, only 1 motion picture and others still sub picture (s) multi search pictures sub picture (s): motion or still sub picture (e): 9 or 12 still pictures, strobe display or only 1 motion picture and others still. main picture sub picture (s) sub picture (s) sub picture (s) 3-picture pop display sub picture: 4:3 aspect ratio still, strobe, only 1 motion picture main picture: display using tc90a18af (edwac) pip display sub picture (s) main picture sub picture: 16:9 or 4:3 aspect ratio motion or still main picture: display using tc90a18af (edwac)
TC90A66F 2001-06-07 15 i 2 c bus address setting table sub address msb lsb cc%c8 dec 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 0 myph2 1 0 myqph0 rrstinv rckinv rreph1 0 m4m2 sesw 01 1 ysbact fraclr yscclr ysbclr ysaclr 02 2 mblkiq7 6 5 4 3 2 1 0 mblky7 6 5 4 3 2 1 0 03 3 mmwiq7 6 5 4 3 2 1 0 mmwy7 6 5 4 3 2 1 0 04 4 05 5 06 6 07 7 08 8 09 9 rhysae11 10 9 8 7 6 5 4 3 2 1 0 0a 10 rhysas11 10 9 8 7 6 5 4 3 2 1 0 0b 11 rvysae9 8 7 6 5 4 3 2 1 0 0c 12 rvysas9 8 7 6 5 4 3 2 1 0 0d 13 rhysbe11 10 9 8 7 6 5 4 3 2 1 0 0e 14 rhysbs11 10 9 8 7 6 5 4 3 2 1 0 0f 15 rvysbe9 8 7 6 5 4 3 2 1 0 10 16 rvysbs9 8 7 6 5 4 3 2 1 0 11 17 rhysce11 10 9 8 7 6 5 4 3 2 1 0 12 18 rhyscs11 10 9 8 7 6 5 4 3 2 1 0 13 19 rvysce9 8 7 6 5 4 3 2 1 0 14 20 rvyscs9 8 7 6 5 4 3 2 1 0 15 21 rhsiz11 10 9 8 7 6 5 4 3 2 1 0 16 22 rvsiz9 8 7 6 5 4 3 2 1 0 17 23 roefon rgame dwsw rrh11 10 9 8 7 6 5 4 3 2 1 0 18 24 frfi roealt rfisw rfalt rrv9 8 7 6 5 4 3 2 1 0 note2: set 0 in blank columns.
TC90A66F 2001-06-07 16 sub address msb lsb cc%c8 dec 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 25 rw rn9 8 7 6 5 4 3 2 1 0 1a 26 rwra9 8 7 6 5 4 3 2 1 0 1b 27 rhrfth rhrfiv rhinv2 rckchg prhp11 10 9 8 7 6 5 4 3 2 1 0 1c 28 rpllph11 10 9 8 7 6 5 4 3 2 1 0 1d 29 dwfil jswap whst10 9 8 7 6 5 4 3 2 1 0 1e 30 whmod3 2 1 0 wckinv whed10 9 8 7 6 5 4 3 2 1 0 1f 31 weyinv weydl2 1 ieninv kwst10 9 8 7 6 5 4 3 2 1 0 20 32 wecinv wecdl2 1 0 wepcm kwed10 9 8 7 6 5 4 3 2 1 0 21 33 whrfth whrfiv whinv2 moh shrst11 10 9 8 7 6 5 4 3 2 1 0 22 34 pcmain siqinv eiqinv ehrst11 10 9 8 7 6 5 4 3 2 1 0 23 35 wckeon phref11 10 9 8 7 6 5 4 3 2 1 0 24 36 sclpst7 6 5 4 3 2 1 0 sclped7 6 5 4 3 2 1 0 25 37 eclpst7 6 5 4 3 2 1 0 eclped7 6 5 4 3 2 1 0 26 38 wplhs eplhs ehinv evinv ntpal rplhs hdwdt7 6 5 4 3 2 1 27 39 whihyo wkhyo whinv wvinv ws262 hyj3 2 1 wvmsk7 6 5 4 3 woerstn ehihyo ekhyo 28 40 rhihyo rkhyo rhinv rvinv rs262 hij3 2 1 rvmsk7 6 5 4 3 2 1 0 29 41 jvlochg jfmint jvloinv wkyfrm mainrst mskoff vfiloff wvst8 7 6 5 4 3 2 1 0 2a 42 jwrton poeinv int3s2 rstdel wved8 7 6 5 4 3 2 1 0 2b 43 field vspd1 0 jvscrl vl8 7 6 5 4 3 2 1 0 2c 44 mwback bvie5 4 3 2 1 0 bvwe8 7 6 5 4 3 2 1 0 2d 45 mult strend vskoff kskoff randm hie9 8 7 6 5 4 3 2 1 0 2e 46 bhie5 4 3 2 1 0 kjh9 8 7 6 5 4 3 2 1 0 2f 47 bvrn3 2 1 0 bhrn3 2 1 0 kjv7 6 5 4 3 2 1 0 30 48 atmv3 2 1 0 atmh3 2 1 0 atfld7 6 5 4 3 2 1 0 31 49 stmv3 2 1 0 stmh3 2 1 0 stvs7 6 5 4 3 2 1 0 32 50 atstrv atstrh at2chg sths9 8 7 6 5 4 3 2 1 0 note2: set 0 in blank columns.
TC90A66F 2001-06-07 17 sub address msb lsb cc%c8 dec 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 33 51 chmv3 2 1 0 chmh3 2 1 0 atlv3 2 1 0 atlh3 2 1 0 34 52 rh9 8 7 6 5 4 3 2 1 0 35 53 ycmf2 ycmf1 ycmn c2hft y2hft w1nsel thruy kmode thruyc ydl2 1 0 ktc ktb kta ofset 36 54 kd15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 37 55 kd31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 38 56 hf spaiv ylpfch thruc clpfth ylpfth 39 57 vfn3 2 1 0 vfyth vkos4 3 2 1 0 3a 58 3b 59 sycinv pcmain sthru 3c 60 3d 61 3e 62 3f 63 40 64 fraon bmaskon cbys abys acys 41 65 42 66 43 67 44 68 45 69 46 70 47 71 48 72 49 73 4a 74 4b 75 4c 76 note2: set 0 in blank columns.
TC90A66F 2001-06-07 18 sub address msb lsb cc%c8 dec 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4d 77 4e 78 4f 79 50 80 51 81 52 82 53 83 54 84 55 85 56 86 57 87 58 88 59 89 5a 90 5b 91 5c 92 5d 93 rhmble11 10 9 8 7 6 5 4 3 2 1 0 5e 94 rhmbls11 10 9 8 7 6 5 4 3 2 1 0 5f 95 rvmble9 8 7 6 5 4 3 2 1 0 60 96 rvmbls9 8 7 6 5 4 3 2 1 0 61 97 mfraiq7 6 5 4 3 2 1 0 mfray7 6 5 4 3 2 1 0 62 98 63 99 64 100 rmhcnt11 10 9 8 7 6 5 4 3 2 1 0 65 101 rmvcnt9 8 7 6 5 4 3 2 1 0 66 102 rmhtes10 9 8 7 6 5 4 3 2 1 0 note2: set 0 in blank columns.
TC90A66F 2001-06-07 19 sub address msb lsb cc%c8 dec 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 67 103 rmvtes8 7 6 5 4 3 2 1 0 68 104 rmhmov6 5 4 3 2 1 0 69 105 rmwsel rmvmov6 5 4 3 2 1 0 6a 106 yscmvon ysamvon ysbmvon rhmdn rmhup rmvsel4 3 2 1 rmhsel4 3 2 1 6b 107 fhwe3 2 1 0 rhfre11 10 9 8 7 6 5 4 3 2 1 0 6c 108 fhws3 2 1 0 rhfrs11 10 9 8 7 6 5 4 3 2 1 0 6d 109 fvwe3 2 1 0 fheon fhson rvfre9 8 7 6 5 4 3 2 1 0 6e 110 fvws3 2 1 0 fveon fvson rvfrs9 8 7 6 5 4 3 2 1 0 6f 111 70 112 71 113 72 114 73 115 74 116 75 117 76 118 77 119 78 120 79 121 7a 122 7b 123 7f 127 autoin note2: set 0 in blank columns.
TC90A66F 2001-06-07 20 outline of i 2 c bus control format i 2 c bus control for the tc90a31f conforms to the philips format. data transfer format s: start condition p: stop condition a: acknowledge (1) start and stop conditions (2) bit transfer sda scl sda may be changed. do not change sda. data are valid only when clock pulse = h (including rising/falling edges). sda scl s start condition p stop condition when clock line = h, defined at the falling edge of data line. when clock line = h, defined at the rising edge of data line. 7-bit 8-bit 8-bit msb msb msb s slave address 0 a sub address a xxxxxxxx a xxxxxxxx a p 8-bit msb
TC90A66F 2001-06-07 21 (3) acknowledge (4) slave address a6 a5 a4 a3 a2 a1 a0 r/w 0 0 1 0 0 1 1 0 purchase of toshiba i 2 c components conveys a license under the philips i 2 c patent right to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. high impedance sda from maste r s 8 1 sda from slave scl from master 9 high impedance
TC90A66F 2001-06-07 22 i 2 c bus functions (write) sub address hex dec data signal name function 1d 29 15 dwfil image compression switching pap (l) image compression (h) 14 jswap memory write control s/e inversion inversion (h) (used at right-and-left picture swapping) 10-0 whst10-0 horizontal write start position 1e 30 15-12 whmod3-0 horizontal reduction ratio 1/16 (0h) 1/8 (1h) 1/5 (2h) 1/4 (3h) 1/3 (4h) 3/8 (5h) 2/5 (6h) 1/2 (7h) 3/5 (8h) 5/8 (9h) 2/3 (ah) 3/4 (bh) 4/5 (ch) 7/8 (ch) 15/16 (eh) 16/16 (fh) 11 wckinv memory wck phase inversion inversion (h) 10-0 whed10-0 horizontal write stop position 1f 31 15 weyinv memory y-signal we polarity inversion polarity inversion (h) 13-12 weydl1-0 memory y-signal we delay adjustment delay 0 (0) delay 1 (1) delay 2 (2) delay-1 (3) 11 ieninv memory ie polarity inversion polarity inversion (h) 10-0 kwst10-0 horizontal filter processing start position 20 32 15 wecinv memory c-signal we polarity inversion polarity inversion (h) 14 wecdl2 normal (l) when 2m memory mode h3/4 (whmod3-0 = bh) is set (h) 13-12 wecdl1-0 memory c-signal we delay adjustment delay 0 (0) delay 1 (1) delay 2 (2) delay-1 (3) 11 wepcm memory we for 1-picture 1-picture processing (h) 10-0 kwed10-0 horizontal filter processing stop position 21 33 15 whrfth href signal through function phase comparison (l) through (h) 14 whrfiv polarity inversion of href signal polarity inversion (h) 13 whinv2 polarity inversion of hd signal for phase comparison polarity inversion (h) 12 moh field memory use signal ycs (l) pap ic (h) 11-0 shrst11-0 s-system horizontal phase reference 22 34 15 pcmain 1-picture processing 1-picture processing (h) 14 siqinv 2m memory s system/4m memory-i/q inversion i/q inversion (h) 13 eiqinv 2m memory e system-i/q inversion i/q inversion (h) 11-0 ehrst11-0 e-system horizontal phase reference 23 35 12 wckeon e-system operating control e-system operation (h) 11-0 phref11-0 pll divider counter cycle for write ntsc4m/2m [95d] 24 36 15-8 sclpst7-0 s-system clamp pulse start position 7-0 sclped7-0 s-system clamp pulse stop position (start setting value < stop setting value) 25 37 15-8 eclpst7-0 e-system clamp pulse start position 7-0 eclped7-0 e-system clamp pulse stop position (start setting value < stop setting value) 26 38 15 wplhs through function for s-system phase comparison hd signal through (h) 14 eplhs through function for e-system phase comparison hd signal through (h) 13 ehinv e-system hd polarity inversion at negative polarity input (l) polarity inversion (h) 12 evinv e-system vd polarity inversion at negative polarity input (l) polarity inversion (h) 11 ntpal ntsc/pal switching for typical detector circuit ntsc (l) pal (h) 7 rplhs through function for phase comparison hd signal for read through (h) 6-0 hdwdt7-1 pulse width adjustment function for phase comparison hd signal for read (change in units of w1ck)
TC90A66F 2001-06-07 23 sub address hex dec data signal name function 27 39 15 whihyo s-system forced non-standard forced non-standard (h) 14 wkhyo s-system forced standard forced standard (h) 13 whinv s-system hd signal polarity inversion at negative polarity i nput (l) polarity inversion (h) 12 wvinv s-system vd signal polarity inversion at negative polarity input (l) polarity inversion (h) 11 ws262 s/e-system odd/even inversion 263 (l) 262 (h) 10-8 hyj3-1 read s/e-system standard inversion slice level 7-3 wvmsk7-3 s/e-system vd masking (each 16 lines) 2 woerstn odd/even generator circuit clear stop 1 ehihyo e-system forced non-standard forced non-standard (h) 0 ekhyo e-system forced standard forced standard (h) 28 40 15 rhihyo forced non-standard for read forced non-standard (h) 14 rkhyo forced standard for read forced standard (h) 13 rhinv horizontal direction (hd) signal polarity inversion for read at negative polarity input (l) polarity inversion (h) 12 rvinv vertical direction (vd) signal polarity inversion for read at negative polarity input (l) polarity inversion (h) 11 rs262 odd/even inversion for read 263 (l) 262 (h) 10-8 hij3-1 s/e-system non-standard decision inversion slice level for read 7-0 rvmsk7-0 vd masking for read (each two lines) 29 41 15 jvlochg change of vertical reduction center center of gravity change (h) 14 jfmint field memory initialize initialize (h) 13 jvloinv change of vertical reduction center direction normal (h) 12 wkyfrm forced frame write processing forced frame (h) 11 mainrst memory reset switching at 1-picture processing 1-picture processing (h) 10 mskoff vd masking function off during we vd mask off (h) 9 vfiloff fixed to l 8-0 wvst8-0 vertical write start line 2a 42 15 jwrton write on/off still (l) live (h) 14 poeinv fixed to l 13 int3s2 memory initialize width change 3v (l) 2v (h) 9 rstdel fixed to l 8-0 wved8-0 vertical write stop line 2b 43 15 field only 1-field write 1-field (h) 14-13 vspd1-0 scroll down speed change 12 jvscrl scroll down on/off off (l) on (h) 8-0 vl8-0 number of lines to be moved for vertical reduction center normal [001h] 2c 44 15 mwback background on/off off (l) on (h) 14-9 bvie5-0 [2ch: mwback = 1] block vertical interval 8-0 bvwe8-0 [2ch: mwback = 1] number of block lines
TC90A66F 2001-06-07 24 sub address hex dec data signal name function 2d 45 15 mult multi-search strobe function on/off on (h) 14 strend fixed to l 13 vskoff [2dh: mult = 1] write block position change function on (l) off (h) when set to off, only one picture (upper left) of strobe mode is motion picture. (effective for atstrv, h = 1) 12 kskoff [2dh: mult = 1] reference skip function off on (l) off (h) 10 randm fixed to l 9-0 hie9-0 [2dh: mult = 1] horizontal skip width [2ch: mwback = 1] number of block pixels 2e 46 15-10 bhie5-0 [2ch: mwback = 1] block horizontal interval 9-0 kjh9-0 [2dh: kskoff = 0] reference skip horizontal position 2f 47 15-12 bvrn3-0 [2ch: mwback = 1] number of vertical blocks (setting value: number of vertical blocks ? 1) 11-8 bhrn3-0 [2ch: mwback = 1] number of horizontal blocks (setting value: number of horizontal blocks ? 1) 7-0 kjv7-0 [2dh: kskoff = 0] reference skip vertical position 30 48 15-12 atmv3-0 number of strobe mode vertical blo cks (setting value: number of vertical blocks ? 1) 11-8 atmh3-0 number of strobe mode horizontal blo cks (setting value: number of horizontal blocks ? 1) 7-0 atfld7-0 [2dh: mult = 1] write field interval (00h = 2fi, 01h = 4fi :/:/:/ ) 31 49 15-12 stmv3-0 [2dh: mult = 1] vertical block position for 1 motion picture (specified block ? 1) 11-8 stmh3-0 [2dh: mult = 1] horizontal block position for 1 motion picture (specified block ? 1) 7-0 stvs7-0 [2dh: mult = 1] number of vertical block lines 32 50 13 atstrv [2dh: mult = 1] vertical strobe function multi search (l) strobe (h) 12 atstrh [2dh: mult = 1] horizontal strobe function multi search (l) strobe (h) 11 at2chg [2dh: mult = 1] strobe vertical 2-row write function on (h) 9-0 sths9-0 [2dh: mult = 1] number of horizontal block pixels (setting value: number of block pixels ? 3) 33 51 15-12 chmv3-0 [32h: at2chg = 1] strobe row 2 11-8 chmh3-0 [32h: at2chg = 1] strobe line 2 7-4 atlv3-0 [32h: at2chg = 1] strobe row 1 3-0 atlh3-0 [32h: at2chg = 1] strobe line 1 34 52 9-0 rh9-0 [2dh: mult = 1] number of multi search horizontal pixels (setting value: horizontal pixels ? 3) = 15h: field memory horizontal read size in multi search, strobe mode number of pixels = (number of block pixels) (number of horizontal blocks) 35 53 15 ycmf2 ycmix signal (m/n type) polarity inversion polarity inversion (h) 14 ycmf1 ycmix signal (before multiplier) polarity inversion polarity inversion (h) 13 ycmn compression switching m/n compression (l) 1/n compression (h) 12 c2hft color signal (i/q) binary interpolation circuit on/off on (h) 11 y2hft luminance signal binary interpolation circuit on/off on (h) 10 w1nsel reduction processor circuit switching m/n (l) 1/n (h) 9 thruy through output on/off for y-signal only on (h) 8 kmode horizontal filter coefficient mode switching 1/n processing (l) m/n processing (h) 7 thruyc [35h: ycmn = 1] horizontal filter through on/off on (h) 6-4 ydl2-0 y signal delay adjustment 3-1 ktc-a number of filter coefficients 0hex = 1, 1hex = 2, :/:/:/ 7hex = 8 0 ofset fixed to l
TC90A66F 2001-06-07 25 sub address hex dec data signal name function 36 54 15-0 kd15-0 horizontal filter coefficient 1 (kd 3-0)~coefficient 8 (kd31-28) 37 55 15-0 kd31-16 1/n compression: 10h-setting value (complement) m/n compression: hex 38 56 7 hfspaiv [4m mode] polarity inversion of y/c separation control signal before hfil stage polarity inversion (h) 3 ylpfch lpf for y signal switching stage 2 (l) stage 1 (h) 2 thruc c-signal-only through output on/off on (h) 1 clpfth lpf for c signal on/off on (h) 0 ylpfth lpf for y signal on/off on (h) 39 57 11-8 vfn3-0 vertical compression ratio (setting value: denominator C 1) (1/2 1, 1/3 2, 1/4 3, 3/4 3, 1/5 ? 4, 1/6 5, 1/8 7) select from the above reduction ratios. 5 vfyth vertical filter through on/off on (h) 4-0 vkos4-0 ram address specification for vertical filter coefficient set according to the specified vertical reduction ratio as follows: 1/3 (00h), 1/4 (03h), 1/2 (07h), 3/4 (09h), 5/6 (0dh), 1/8 (13h), 1/5 (1bh) 3b 59 11 sycinv polarity inversion of y/c separation control signal polarity inversion (h) 10 pcmain 1-picture processing 1-picture processing (h) 8 sthru sel block through on/off on (h) 7f 127 8 autoin vertical filter sram data transmission auto increment mode [h] set to l for no vertical reduction.
TC90A66F 2001-06-07 26 i 2 c bus functions (read) sub address hex dec data signal name function 00 00 15-13 myph2-0 y signal phase adjustment for read 12 miqph0 i/q signal phase adjustment for read 11 rrstinv polarity inversion of field memory read reset (rrst) signal inversion (h) 10 rckinv polarity inversion of field memory read clock (pck) signal inversion (h) 9-8 rreph1-0 phase adjustment of field memory read enable (rre) signal inversion (h) 7 m4m2 4m memory/2m memory mode switching 4m (l) 2m (h) 6 sesw s/e system control switching s system (l) e system (h) 01 01 13 ysbact ys off (l) on (h) 12 fraclr frame signal off (l) on (h) 11 yscclr ys (e system) off (l) on (h) 10 ysbclr ys (external) off (l) on (h) 9 ysaclr ys (s system) off (l) on (h) 02 02 15-12 mblkiq7-4 blanking level (i) 11-8 mblkiq3-0 blanking level (q) 7-0 mblky3-0 blanking level (y) 03 03 15-12 mmwiq7-0 background level (i) 11-8 mmwiq3-0 background level (q) 7-0 mmwy7-0 background level (y) 09 09 11-0 physae11-0 ys horizontal stop position (s system) 0a 10 11-0 physas11-0 ys horizontal start position (s system) 0b 11 9-0 rvysae9-0 ys vertical stop position (s system) 0c 12 9-0 rvysas9-0 ys vertical start position (s system) 0d 13 11-0 rhysbe11-0 ys horizontal stop position (external) 0e 14 11-0 rhysbs11-0 ys horizontal start position (external) 0f 15 9-0 rvysbe9-0 ys vertical stop position (external) 10 16 9-0 rvysbs9-0 ys vertical start position (external) 11 17 11-0 rhysce11-0 ys horizontal stop position (e system) 12 18 11-0 rhyscs11-0 ys horizontal start position (e system) 13 19 9-0 rvysce9-0 ys vertical stop position (e system) 14 20 9-0 rvyscs9-0 ys vertical start position (e system) 15 21 11-0 rhsiz11-0 field memory horizontal read size (set number of horizontal pixels ? 3) 16 22 9-0 rvsiz9-0 field memory read size (vertical) 17 23 14 roefon field memory read/write phase control for write on (h) 13 rgame game mode display on (h) 12 dwsw pip display (vertical 1/2 size or smaller) pip (h) 11-0 rrh11-0 field memory horizontal read start position 18 24 15 frfi field/frame display switching frame (l) field (h) 14 roealt odd/even switching 13 rfisw field/frame display switching (field memory read/write phase control on/off) frame (h) field (l) 12 rfalt field memory read/write phase control at memory read normal (h) 9-0 rrv9-0 field memory vertical read start position
TC90A66F 2001-06-07 27 sub address hex dec data signal name function 19 25 9-0 rwrn9-0 field memory read/write phase control start (at standard) 1a 26 9-0 rwra9-0 field memory read/write phase control start (at non-standard) 19h and 1ah are control registers at frame display (pip, dw). 19h is for when main/sub picture is standard signal; 1ah is for when either main/sub picture is non-standard signal. how to calculate the setting value: sub address 15h: field memory horizontal read size = a sub address 16h: field memory vertical read size = b (calculate in decimal) input the result of the above calculation in hexadecimal (19h and 1ah have the same value). 1b 27 15 rhrfth control output mode for rhref signal output control forced output (h) 14 rhrfiv polarity inversion of rhref signal polarity inversion (h) 13 rhinv2 hd polarity inversion of rhref signal output control polarity inversion (h) 12 rckchg read clock switching normal (l) 11-0 prhp11-0 read horizontal reference (pll counter decoded value) 1c 28 11-0 rpllph11-0 pll counter for read (fh setting) 40 64 6 fraon frame signal off (l) on (h) 5 bwaskon background/image switching background (l) image (h) (set background to yiq level at 03h.) 2 cbys ysb > ysc (l) ysb < ysc (h) (ysa: s system, ysb: external, ysc: e system) 1 abys ysa > ysb (l) ysa < ysb (h) 0 acys ysa > ysc (l) ysa < ysc (h) 5d 93 11-0 rhmble11-0 blanking horizontal stop position 5e 94 11-0 rhmbls11-0 blanking horizontal start position 5f 95 9-0 rvmble9-0 blanking vertical stop position 60 96 9-0 rvmbls9-0 blanking vertical start position 61 97 15-12 mfraiq7-4 frame level (i) 11-8 mfraiq3-0 frame level (q) 7-0 mfray7-0 frame level (y) 64 100 11-0 rmhcnt11-0 wipe signal horizontal reference (center) 65 101 9-0 rmvcnt9-0 wipe signal vertical reference (center) 66 102 10-0 rmhtes10-0 wipe signal horizontal phase range (width) 67 103 8-0 rmvtes8-0 wipe signal vertical phase range (width) 68 104 6-0 rmhmov6-0 wipe signal horizontal operating speed 69 105 15 rmwsel wipe signal system select window (l) cross (h) 6-0 rmvmov6-0 wipe signal vertical operating speed (a + 3) b ? 600 256
TC90A66F 2001-06-07 28 sub address hex dec data signal name function 6a 106 15 yscmvon e-system wipe off (l) on (h) 11 ysamvon s-system wipe off (l) on (h) 10 ysbmvon external wipe off (l) on (h) 9 rmhdn wipe counter up (l) down (h) 8 rmhup wipe counter reset reset (l) 7 rmvsel4 vertical wipe (top) off (l) on (h) 6 rmvsel3 vertical wipe (bottom) off (l) on (h) 5 rmvsel2 fixed to h 4 rmvsel1 fixed to l 3 rmhsel4 horizontal wipe (right) off (l) on (h) 2 rmhsel3 horizontal wipe (left) off (l) on (h) 3-2 rmhsel2 fixed to h 1-0 rmhsel1 fixed to l 6b 107 15-12 fhwe3-0 frame horizontal width (stop position) 11-0 rhfre11-0 frame horizontal stop position 6c 108 15-12 fhws3-0 frame horizontal width (start position) 11-0 rhfrs11-0 frame horizontal start position 6d 109 15-12 fvwe3-0 frame vertical width (stop position) 11 fheon frame horizontal (stop position) off (l) on (h) 10 fhson frame horizontal (start position) off (l) on (h) 9-0 rvfre9-0 frame vertical stop position 6e 110 15-12 fvws3-0 frame vertical width (start position) 11 fveon frame vertical (stop position) off (l) on (h) 10 fvson frame vertical (start position) off (l) on (h) 9-0 rvfrs9-0 frame vertical start position
TC90A66F 2001-06-07 29 description of i 2 c bus data for read 1. frame display (1) y signal can be set with 8-bit precision; i/q signal with 4-bit precision. (2) frame width can be set in 4 bits (16 types). (3) set frame details using the following registers: rhfrs: frame horizontal start position rhfre: frame horizontal stop position fhws: frame horizontal width (start position) fhwe: frame horizontal width (stop position) rvfrs: frame vertical start position rvfre: frame vertical stop position fvws: frame vertical width (start position) fvwe: frame vertical width (stop position) 2. ys and blanking setting (1) set the ys signal timing using the following registers. (2) set horizontal start and stop positions, and vertical start and stop positions for blanking. ys horizontal start position (s system) ys vertical start position (e system) ys horizontal stop position (s system) ys vertical stop position (e system) ys horizontal start position (e system) blanking horizontal start position ys horizontal stop position (e system) ! blanking horizontal stop position ys vertical start position (s system) " blanking vertical start position ys vertical stop position (s system) # blanking vertical stop position fvws fhwe phfrs fvwe rvfre sub picture rvfrs fhws rhfre sub picture (s) sub picture (e) ! # rhyscs blanking rhysce physas physae rvyscs rvysce rvysas rvysae blanking "
TC90A66F 2001-06-07 30 settings of special effect functions 3. scroll down special effect function used when selecting 2-picture, 1-picure, or pip display. the function freezes the image signal before selection then moves the image after selection from the top. (1) 1-field display 18h (24) frfi & = h (field display) frisw $ = l (field display) (2) write stop 2ah (42) jwrton & = l (write stop) (3) select channel change start change channel after write actually stopped. (4) scroll down function environment setting 29h (41) mainrst " = h wkyfrm # = h 2bh (43) field & = h (5) scroll down start 2bh (43) jvscrl # = h (6) write start 2ah (42) jwrton & = h (7) scroll down standby time (do not change frame processing during standby) 2bh: vspd setting value number of write lines ntsc (240 valid lines) pal (282 valid lines) ll 2 120fr (4.0 s) 141fr (5.6 s) lh 4 60fr (2.0 s) 70fr (2.8 s) hl 6 40fr (1.3 s) 47fr (1.9 s) hh 7 34fr (1.1 s) 40fr (1.6 s) (8) write processing change (frame processing) 29h(41) wkyfrm # = l (after 1 field) 29h(41) mainrst " = l 2bh(43) field & = l jvscrl # = l (9) read processing change (frame processing) after sending write processing data, count four fields of vd for read, then send the following data. (after new image signal is written to memory, frame is displayed.) 18h (24) frfi & = l frisw $ = h
TC90A66F 2001-06-07 31 settings of special effect functions 4. wipe function (1) wipe on/off 6ah (106) yscmvon & e system wipe on (h)/off (l) ysamvon " s system wipe on (h)/off (l) ysbmvon ! external wipe on (h)/off (l) (2) wipe signal center and width settings (horizontal and vertical) 64h (100) rmhcnt wipe signal horizontal reference (center) 65h (101) rmvcnt wipe signal vertical reference (center) 66h (102) rmhtes wipe signal horizontal phase adjustment (width) 67h (103) rmvtes wipe signal vertical phase adjustment (width) (3) wipe signal speed settings (count number of vertical sync signal) 68h (104) rmhmov wipe signal horizontal operating speed large slow small fast 69h (105) rmvmov wipe signal vertical operating speed large slow small fast (4) wipe direction setting 6ah (106) rmvsel4 up on (h)/off (l) rmvsel3 down on (h)/off (l) rmhsel4 right on (h)/off (l) rmhsel3 left on (h)/off (l) (5) wipe type setting 69h (105) rmwsel window (l) cross (h) (6) wipe operating control 6ah (106) rmhdh wipe counter up (l)/down (h) rmhup wipe counter reset reset (l) (1) start from wipe close rmhdn = l, rmhup = l (wipe close: initial state) rmhdn = l, rmhup = h rmhdn = h, rmhup = h (wipe open) (2) start from wipe open rmhdn = h, rmhup = l (wipe open: initial state) rmhdn = h, rmhup = h rmhdn = l, rmhup = h (wipe close) * : send in order of to . * : when the center is changed, make initial settings. window cross
TC90A66F 2001-06-07 32 maximum ratings (v ss = = = = 0 v, ta = = = = 25c) characteristics symbol rating unit power supply voltage v ss , v dd v ss to v ss + 4.0 v v in1 ? 0.3 to v dd + 0.3 input voltage v in2 ? 0.3 to 525 (note3) v power dissipation p d (note4) 2000 mw storage temperature t stg ? 55 to 125 c note3: applicable to wvde, whde, wcke, wvds, whds, wcks, rdac0 to rdac7, rday0 to rday7, rck, rhd, rvd, scl, and sda pins. note4: when using the ic at ta = 25 c or higher, reduce 20.0 mw per degree. power dissipation reduction against higher temperature (when mounted on board) recommended operating conditions (v ss = = = = 0 v) characteristics symbol test condition min typ. max unit power supply voltage v dd ? 3.0 3.3 3.6 v input voltage v in ? 0 ? v dd v operating temperature t opr ? ? 20 ? 70 c operating temperature ( c) power dissipation (mw) 1500 125 50 0 25 70 100 500 1100 500 2000
TC90A66F 2001-06-07 33 electrical characteristics 1. dc characteristics operating conditions: v dd = = = = 3.0 to 3.6 v, v in = = = = 0 to v dd , ta = = = = ? ? ? ? 20 to 70c, v ss = = = = 0 characteristics symbol test circuit test condition min typ. max unit terminal power dissipation i dd ? ntsc ? ? 250 ma v dd 0.8 ? v dd (note5) cmos input v dd 0.8 ? 5.25 (note9) high-level input voltage schmitt trigger input v ih ? ? v dd 0.8 ? 5.25 v (note6) cmos input ? ? v dd 0.2 (note5) ? ? v dd 0.2 (note9) low-level input voltage schmitt trigger input v il ? ? ? ? v dd 0.2 v (note6) high level i ih ? v in = v dd ? 10 ? 10 (note5) input current low level i il ? v in = v ss ? 10 ? 10 a (note6) v oh1 i oh1 = ? 4 ma 2.4 ? (note7) high level v oh2 i oh2 = ? 8 ma 2.4 ? (note8) v ol1 i ol1 = 4 ma ? ? 0.4 (note7) output voltage low level v ol2 ? i ol2 = 8 ma ? ? 0.4 v (note8) schmitt trigger hysteresis voltage v h ? ? ? 0.5 v (note6) note5: tin9-0, rmcki, pwrst, timrst, iicnr, sadsel, tst4-0, whrefe, whrefs, ewien, ewen, ewrst, wien, wen, wrst, wdac7-0, wday7-0, ren, rrst, eren, errst, rhref, t107-100, ewmck, wmck, rmck note6: wvde, whde, wvds, whds, rhd, rvd, scl, sda note7: whrefe, whrefs, ewien, ewen, ewrst, wien, wen, wrst, wdac7-0, wday7-0, ren, rrst, eren, errst, rhref, sda, t107-100, ewmck, wmck, rmck note8: ewmck, wmck, rmck note9: wcke, wcks, rdac0-7, rday0-7, rck
TC90A66F 2001-06-07 34 2. ac characteristics operating conditions: v dd = = = = 3.3 to 3.6 v, v in = = = = 0 to v dd , ta = = = = ? ? ? ? 20 to 70c, v ss = = = = 0 characteristics symbol test circuit test condition min typ. max unit re- marks operating frequency condition ? ntsc mode 20 ? mhz tsup1 5 ? ? input setup time tsup2 ? operating frequency: 20 mhz 5 ? ? ns thld1 3 ? ? input hold time thld2 ? operating frequency: 20 mhz 5 ? ? ns tpd1 5 ? 20 tpd2 4 ? 16 tpd3 6 ? 22 tpd4 6 ? 18 tpd5 6 ? 21 tpd6 6 ? 17 tpd7 6 ? 21 tpd8 6 ? 17 tpd9 7 ? 24 tpd10 6 ? 22 tpd11 6 ? 22 tpd12 6 ? 19 tpd13 6 ? 22 tpd14 6 ? 19 tpd15 4 ? 18 tpd16 4 ? 15 tpd17 6 ? 20 tpd18 5 ? 17 tpd19 6 ? 20 output transfer delay time tpd20 ? cl = 10.8 pf vth = 2 v wck = 37.8 mhz rck = 37.8 mhz 6 ? 17 ns 3. 1 adc characteristics operating conditions: v dd = = = = 3.3 v, ta = = = = ? ? ? ? 20 to 70c, v ss = = = = 0 characteristics symbol test circuit test condition min typ. max unit non-linear error ile ? v dd = 3.3 v dack = 10 mhz ? 3 ? + 3 lsb differential non-linear error dle ? v dd = 3.3 v dack = 10 mhz ? 2 ? + 2 lsb full sca vifs ? v dd = 3.3 v dack = 10 mhz ? 2.2 ? v analog input voltage zero sca vizs ? v dd = 3.3 v dack = 10 mhz ? 1.1 ? v
TC90A66F 2001-06-07 35 3. 2 clamp and multiplexer operating conditions: v dd = = = = 3.3 v, ta = = = = ? ? ? ? 20 to 70c, v ss = = = = 0 characteristics symbol test circuit test condition min typ. max unit clamp y ? ? ? ? 63 ? lsb clamp c ? ? ? ? 136 ? lsb multiplexer ? ? ? ? 5 ? mhz 4. dac characteristics operating conditions: v dd = = = = 3.3 v, ta = = = = ? ? ? ? 20 to 70c, v ss = = = = 0 characteristics symbol test circuit test condition min typ. max unit non-linear error ile ? v dd = 3.3 v dack = 20 mhz ? 3 ? + 3 lsb differential non-linear error dle ? v dd = 3.3 v dack = 20 mhz ? 2 ? + 2 lsb full sca vifs ? v dd = 3.3 v dack = 20 mhz ? ? v dd v analog input voltage zero sca vizs ? v dd = 3.3 v dack = 20 mhz v ref ? ? v
TC90A66F 2001-06-07 36 ac characteristic timing charts write read wmck wrst weny wenc wie wday 7 to 0 wck tpd1 tpd3 tpd5 tpd7 tpd9 tpd11 tpd13 tpd2 tpd4 tpd6 tpd8 tpd10 tpd12 tpd14 wdac 7 to 0 tpd17 tpd16 tpd19 tpd18 tpd20 tpd15 rmck rrst ren rmcki rday 7 to 0 rck rdac 7 to 0 thld1 tsup1 thld2 tsup2
TC90A66F 2001-06-07 37 application circuit (c/e) 5.1 k ? 0.1 f 2 k ? adv dd yins iins adv ss adv dd qins vrty adv ss vrby vrtc vrbc adv dd yine iine adv ss av dd qine av ss v dd cnt2 cnt1 cnt0 clamp tin9 tin8 tin7 tin6 tin5 tin4 tin3 tin2 tin1 tin0 wvde whde v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0.1 f 10 f adbias 144 vref 143 vb1 142 vb2 141 qout 140 dav dd 139 iout 138 dav ss 137 yout 136 dav dd 135 v ss 134 cnt3 133 cnt4 132 cnt 5 131 cnt6 130 t100 129 t101 128 t102 127 t103 126 t104 125 t10 5 124 t106 123 t107 122 v dd 21 test0 120 test1 119 test2 118 test3 117 test4 116 sda 115 sc l 114 v ss 113 sacn 112 sadse l 111 iicn r 110 teso 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 wcke whrefe v dd hrst moh wvds whds v ss wcks whrefs v dd ewmck v ss wmck v ss ewien ewen ewrst wien wen wrst wdac7 wdac6 wdac5 wdac4 wdac3 wdac2 wdac1 wdac0 v ss wday7 wday6 wday5 wday4 wday3 wday2 timrst pwrst hyojun kays ys rvd rhd v dd rck rhref rmcki v ss rmck errst eren rrst ren rday7 rday6 rday5 rday4 rday3 rday2 rday1 rday0 v dd rdac7 rdac6 rdac5 rdac4 rdac3 rdac2 rdac1 rdac0 wday0 wday1 8 9 10 11 12 13 14 7 6 5 4 3 2 1 (e) 3 k ? 560 ? 0.1 f 10 f 0.1 f 0.1 f 10 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 10 f 0.1 f 0.1 f 10 f 0.1 f 10 f 100 f 100 f 5 4 3 2 1 3.3 pf 27 k ? wvde whde whds wvds 0.1 f 2 k ? 8 9 10 11 12 13 14 7 6 5 4 3 2 1 (s) 3 k ? 560 ? 0.1 f 10 f 0.1 f 100 f 100 f 3 1 5 4 2 27 k ? 3.3 pf 15 17 19 21 23 25 27 16 18 20 22 24 26 28 2 4 6 8 10 12 14 1 3 5 7 9 11 13 0.1 f 1 k ? 0.1 f 0.1 f 0.1 f 10 f 10 f 2.2 k ? qine iine yine qins iins yins qout iout yout 3.3 v gnd tp 10 f 10 f 10 f scl sda msm51v8221 tlc2933 tc7508f (and) tlc2933 tc7508f (and) TC90A66F 10 f 560 ? 10 f 1 3 5 4 2 3 k ? 3.3 pf 10 f 0.1 f 100 f 0.1 f 27 k ? 0.1 f 100 f tp1 tp2 tp3 10 f rhd rvd ys tlc2933 8 9 10 11 12 13 14 7 6 5 4 3 2 1 tc7508f (inverter) 28 msm51v8221 26 24 22 20 18 16 14 12 10 8 6 4 2 27 25 23 21 19 17 15 13 11 9 7 5 3 1 (y/s) 10 f 2 k ? 2.7 k ? 10 f 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TC90A66F 2001-06-07 38 package dimensions weight: 4.64 g (typ.)
TC90A66F 2001-06-07 39 ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the handling guide for semiconductor devices, or toshiba semiconductor reliability handbook etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (unintended usage). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customers own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eba restrictions on product use

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